library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


entity mux is
port(a,b:in std_logic_vector(2 downto 0);x:out std_logic_vector(5 downto 0));
end entity mux;




architecture bool of mux is
	signal t1,t2,t3,t4,tc1,tc2:std_logic_vector(5 downto 0);
	
	component myand2 is
	port(ina,inb:in std_logic;aband:out std_logic);
	end component myand2;
	component adder1 is
	port(a,b,cin:in std_logic;sum,cout:out std_logic);
	end component adder1;
	
	

begin
	my1:myand2 port map(a(0),b(0),t1(0));
	my2:myand2 port map(a(1),b(0),t1(1));
	my3:myand2 port map(a(2),b(0),t1(2));
	
	my4:myand2 port map(a(0),b(1),t2(1));
	my5:myand2 port map(a(1),b(1),t2(2));
	my6:myand2 port map(a(2),b(1),t2(3));
	
	my7:myand2 port map(a(0),b(2),t3(2));
	my8:myand2 port map(a(1),b(2),t3(3));
	my9:myand2 port map(a(2),b(2),t3(4));	
	
	
	ad1:adder1 port map(t1(0),t2(0),'0',t4(0),tc1(0));
	ad2:adder1 port map(t1(1),t2(1),tc1(0),t4(1),tc1(1));
	ad3:adder1 port map(t1(2),t2(2),tc1(1),t4(2),tc1(2));
	ad4:adder1 port map(t1(3),t2(3),tc1(2),t4(3),tc1(3));
	t4(4) <= tc1(3);
	
	a1:adder1 port map(t4(0),t3(0),'0',x(0),tc2(0));
	a2:adder1 port map(t4(1),t3(1),tc2(0),x(1),tc2(1));
	a3:adder1 port map(t4(2),t3(2),tc2(1),x(2),tc2(2));
	a4:adder1 port map(t4(3),t3(3),tc2(2),x(3),tc2(3));
	a5:adder1 port map(t4(4),t3(4),tc2(3),x(4),tc2(4));
	x(5) <= tc2(4);
	
	
end architecture bool;